Semiconductor devices having sense amplifiers and electronic systems employing the same

ABSTRACT

A semiconductor device having sense amplifiers and an electronic system employing the same are provided. The semiconductor device includes first sense amplifier blocks arranged in a row direction on a substrate and spaced apart from each other by a first distance. A second sense amplifier block spaced apart from the first sense amplifier blocks by a second distance greater than the first distance is provided. A plurality of cell array blocks arranged in the row direction on the substrate is provided. Each of the first and second sense amplifier blocks is disposed between the cell array blocks, and each of the cell array blocks includes a plurality of memory cells.

PRIORITY STATEMENT

This non-provisional U.S. patent application claims priority under 35U.S.C. §119 to Korean Patent Application No. 10-2007-0117926, filed onNov. 19, 2007, the entire contents of which is incorporated herein byreference.

BACKGROUND Description of Related Art

A conventional semiconductor memory device may be provided as aninternal storage region of an electronic product including a computer.For example, conventional semiconductor devices such as DRAM may includea plurality of memory cells and a sense amplifier sensing and amplifyingdata of the memory cells.

SUMMARY

Example embodiments relate to semiconductor devices having senseamplifiers and electronic systems employing the same. Semiconductordevices according to example embodiments may include at least one senseamplifier laid out in a plurality of bit line pitches.

According to at least some example embodiments, a semiconductor devicemay include sense amplifiers. The semiconductor device may include firstsense amplifier blocks arranged in a row direction on a substrate andspaced apart from each other by a first distance. A second senseamplifier block may be spaced apart from the first sense amplifierblocks by a second distance greater than the first distance. A pluralityof cell array blocks may be arranged in the row direction on thesubstrate. Each of the first and second sense amplifier blocks may bedisposed between the cell array blocks, and each of the cell arrayblocks may have a plurality of memory cells.

According to at least some example embodiments, each of the first andsecond sense amplifier blocks may include sense amplifiers arranged in acolumn direction. Bit line pairs may be connected to each of the senseamplifiers and to the same number of memory cells. Each of the senseamplifiers may be connected to 2×(N+1) cell array blocks by the bit linepairs. N may be a positive integer.

At least one other example embodiment provides that the cell arrayblocks may have the same width.

According to at least some example embodiments, a semiconductor deviceincluding sense amplifiers may be connected to a plurality of cell arrayblocks by a bit line pair. The semiconductor device may include mainsense amplifier blocks arranged in a row direction on a substrate,spaced apart from each other, and configured to constitute a main senseamplifier group. Main cell array blocks may be arranged in the rowdirection on the substrate and spaced apart from each other. Main bitline pairs may be configured to connect 2×(N+1) main cell array blocksto each of the main sense amplifier blocks. Each of the main senseamplifier blocks may be disposed between the main cell array blocks. Nmay be a positive integer.

According to at least some example embodiments, each of the main senseamplifier blocks may include main sense amplifiers arranged in a columndirection. The main sense amplifiers may be arranged in a zigzagformation.

At least one example embodiment provides that each of the main senseamplifiers may be laid out in every bit line pitch as many as the numberof main sense amplifier blocks constituting the main sense amplifiergroup. Each of the main sense amplifier blocks may be disposed at themiddle portion of the main bit line pair.

According to at least some example embodiments, the device may furtherinclude an edge sense amplifier group spaced apart from the main senseamplifier group, disposed at one side of the main sense amplifier group,arranged in a row direction on the substrate, and having edge senseamplifier blocks spaced apart from each other. At least one dummy cellarray block may be disposed opposite to the main sense amplifier groupwith the edge sense amplifier group interposed therebetween. An edge bitline pair may be configured to connect N+1 main cell array blocksdisposed in a direction of the main sense amplifier group to the edgesense amplifiers, the dummy cell array block and/or the main cell arrayblock to the edge sense amplifiers.

A dummy bit line, disposed on a virtual extension line of an edge bitline, may be connected only to the main cell array block of the edge bitline pair. Furthermore, the dummy bit line may be connected to the dummycell array block, wherein the dummy bit line may be spaced apart fromthe edge bit line pair.

At least one example embodiment provides that the device may furtherinclude an edge sense amplifier group spaced apart from the main senseamplifier group, disposed at one side of the main sense amplifier groupand arranged in a row direction on the substrate. The edge senseamplifier group may have edge sense amplifier blocks spaced apart fromeach other. A dummy capacitor group may be disposed opposite to the mainsense amplifier group with the edge sense amplifier group interposedtherebetween. An edge bit line pair may be configured to connect N+1main cell array blocks to the edge sense amplifiers, the dummy capacitorgroup to the edge sense amplifiers, and/or connect the main cell arrayblock and the dummy capacitor group to the edge sense amplifiers.

According to at least some example embodiments, a sense amplifier lessarea provided between the main sense amplifier group and the adjacentmain cell array blocks may be included.

At least one example embodiment provides that the main cell array blocksmay include the same number of memory cells.

According to at least some example embodiments, each of the main cellarray blocks may include a cell switching device and a cell data storageelement.

At least some example embodiments provide that an electronic systememploying a semiconductor device that may have sense amplifiers. Theelectronic system may include a processor, an input/output unitconfigured to perform data communication with the processor, and asemiconductor memory device configured to perform data communicationwith the processor. The semiconductor memory device may include firstsense amplifier blocks arranged in a row direction on a substrate andspaced apart from each other by a first distance. A second senseamplifier block may be spaced apart from the first sense amplifierblocks by a second distance greater than the first distance. A pluralityof cell array blocks may be arranged in a row direction on thesubstrate. Each of the first and second sense amplifier blocks may bedisposed between the cell array blocks, and each of the cell arrayblocks may include a plurality of memory cells.

According to at least some example embodiments, each of the first andsecond sense amplifier blocks may include sense amplifiers arranged in acolumn direction. Bit line pairs may be connected to each of the senseamplifiers, wherein the bit line pairs may be connected to the samenumber of memory cells. Each of the sense amplifiers may be connected to2×(N+1) cell array blocks by the bit line pairs. N may be a positiveinteger.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will become more apparent by describing in detailthe example embodiments shown in the attached drawings in which:

FIG. 1 illustrates a semiconductor device according to an exampleembodiment;

FIG. 2 is a circuit diagram of a semiconductor device according to anexample embodiment;

FIGS. 3-5 illustrate semiconductor devices according to other exampleembodiments; and

FIG. 6 is a schematic block diagram of an electronic system according toan example embodiment.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Various example embodiments will now be described more fully withreference to the accompanying drawings in which some example embodimentsare shown. In the drawings, the thicknesses of layers and regions may beexaggerated for clarity.

Detailed illustrative embodiments of the present invention are disclosedherein. However, specific structural and functional details disclosedherein are merely representative for purposes of describing exampleembodiments of the present invention. This invention may, however, maybe embodied in many alternate forms and should not be construed aslimited to only the embodiments set forth herein.

Accordingly, while example embodiments of the invention are capable ofvarious modifications and alternative forms, embodiments thereof areshown by way of example in the drawings and will herein be described indetail. It should be understood, however, that there is no intent tolimit example embodiments of the invention to the particular formsdisclosed, but on the contrary, example embodiments of the invention areto cover all modifications, equivalents, and alternatives falling withinthe scope of the invention. Like numbers refer to like elementsthroughout the description of the figures.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of example embodiments of thepresent invention. As used herein, the term “and/or,” includes any andall combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being“connected,” or “coupled,” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected,” or “directly coupled,” to another element, there are nointervening elements present. Other words used to describe therelationship between elements should be interpreted in a like fashion(e.g., “between,” versus “directly between,” “adjacent,” versus“directly adjacent,” etc.).

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments of the invention. As used herein, the singular forms “a,”“an,” and “the,” are intended to include the plural forms as well,unless the context clearly indicates otherwise. It will be furtherunderstood that the terms “comprises,” “comprising,” “includes,” and/or“including,” when used herein, specify the presence of stated features,integers, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features,integers, steps, operations, elements, components, and/or groupsthereof.

It should also be noted that in some alternative implementations, thefunctions/acts noted may occur out of the order noted in the figures.For example, two figures shown in succession may in fact be executedsubstantially concurrently or may sometimes be executed in the reverseorder, depending upon the functionality/acts involved.

FIG. 1 illustrates a semiconductor device 1 according to an exampleembodiment. Referring to FIG. 1, the semiconductor device 1 may includeM main cell array blocks MCB₁-MCB_(M) arranged in a row direction X on asubstrate. Here, M may be a positive integer. A plurality of memorycells may be provided in each of the main cell array blocksMCB₁-MCB_(M). In the main cell array blocks MCB₁-MCB_(M), the number ofmemory cells arranged in the row direction X may be substantially thesame. Each of the memory cells may include a cell switching device and acell data storage element. For example, in a case of a semiconductormemory device such as a DRAM, the cell data storage element may includea cell capacitor. The cell switching device may be an active device suchas a MOS transistor or a diode.

A first dummy cell array block DCB₁ and a second dummy cell array blockDCB₂ may be provided at both sides of the main cell array blocksMCB₁-MCB_(M) with the main cell array blocks MCB₁-MCB_(M) interposedtherebetween. Each of the first and second dummy cell array blocks DCB₁and DCB₂ may include a plurality of edge memory cells. The edge memorycells may have substantially similar components as the memory cells inthe main cell array blocks MCB₁-MCB_(M). Each of the first and seconddummy cell array blocks DCB₁ and DCB₂ may also include a dummy cellcapacitor and/or a dummy MOS capacitor.

At least one main sense amplifier group MSAG may be provided on thesubstrate. The main sense amplifier group MSAG may be arranged in therow direction on the substrate and include a plurality of main senseamplifier blocks MSAB₁-MSAB₄ spaced apart from each other. Each of themain sense amplifier blocks MSAB₁-MSAB₄ may include a correspondingplurality of main sense amplifiers MSA₁-MSA₄ arranged in a columndirection Y. For example, FIG. 1 illustrates three of each of main senseamplifiers MSA₁-MSA₄.

Each of the main sense amplifiers MSA₁-MSA₄ may be connected to 2×(N+1)main cell array blocks by a corresponding main bit line pair MBL₁-MBL₄.The main sense amplifier MSA₁ may be connected to 2×(N+1) main cellarray blocks by the bit line pair MBL₁. Also, each of the main senseamplifiers MSA₁-MSA₄ may be laid out in every two or more bit linepitches along the column direction Y. The main sense amplifier MSA₁ maybe laid out in every two or more bit line pitches as many as the numberof main sense amplifier blocks constituting one main sense amplifiergroup MSAG. For example, if there are four main sense amplifiersMSA₁-MSA₄, the main sense amplifier MSA₁ may be laid out in every fourthbit line pitch.

In FIG. 1, N may denote a positive integer of 2, and one MSAG mayincludes four main sense amplifier blocks, i.e., the first to fourthmain sense amplifier blocks MSAB₁-MSAB₄. The first to fourth main senseamplifier blocks MSAB₁-MSAB₄ may be sequentially arranged along the rowdirection X.

Each of the main sense amplifier blocks MSAB₁-MSAB₄ may be providedbetween the main cell array blocks MCB₁-MCB_(M). For example, as shownin FIG. 1, each of the main sense amplifier blocks MSAB₁-MSAB₄ may beprovided between main cell array blocks MCB₆-MCB₁₀ selected from themain cell array blocks MCB₁-MCB_(M). As illustrated in FIG. 1, when “N”denotes 2, the main sense amplifier group MSAG may include 4 main senseamplifier blocks, i.e., the first to fourth main sense amplifier blocksMSAB₁-MSAB₄, and each of the first to fourth main sense amplifier blocksMSAB₁-MSAB₄ may be connected to 2×(N+1) main cell blocks, i.e., 6 maincell array blocks, by a main bit line pair. For example, the first mainsense amplifier block MSAB₁ may be connected to 6 main cell arrayblocks, i.e., the fourth to ninth main cell array blocks MCB₄-MCB₉, by afirst main bit line pair MBL₁. Similarly, the second main senseamplifier block MSAB₂ may be connected to 6 main cell array blocks,i.e., the fifth to tenth main cell array blocks MCB₅-MCB₁₀ by a secondmain bit line pair MBL₂, the third main sense amplifier block MSAB₃ maybe connected to 6 main cell array blocks, i.e., the sixth to eleventhmain cell array blocks MCB₆-MCB₁₁ by a third main bit line pair MBL₃,and the fourth main sense amplifier block MSAB₄ may be connected to 6main cell array blocks, i.e., the seventh to twelfth main cell arrayblocks MCB₇-MCB₁₂ by a fourth main bit line pair MBL₄.

The first main sense amplifier block MSAB₁ may include first main senseamplifiers MSA₁ arranged along the column direction Y and the secondmain sense amplifier block MSAB₂ may include second main senseamplifiers MSA₂ arranged along the column direction Y. In addition, thethird main sense amplifier block MSAB₃ may include third main senseamplifiers MSA₃ arranged along the column direction Y, and the fourthmain sense amplifier block MSAB₄ may include fourth main senseamplifiers MSA₄ arranged along the column direction Y.

A first edge sense amplifier group ESAG₁ spaced apart from the mainsense amplifier group MSAG and disposed at one side of the main senseamplifier group MSAG may be provided. Similarly, a second edge senseamplifier group ESAG₂ disposed opposite to the first edge senseamplifier group ESAG₁ with the main sense amplifier group MSAGinterposed therebetween may be provided. Each of the first and secondedge sense amplifier groups ESAG₁ and ESAG₂ may include a plurality ofedge sense amplifier blocks arranged in the row direction X and spacedapart from each other on the substrate. For example, the first edgesense amplifier group ESAG₁ may include first to fourth edge senseamplifier blocks ESAB₁-ESAB₄, and the second edge sense amplifier groupESAG₂ may include fifth to eighth edge sense amplifier blocksESAB₅-ESAB₈. The first and eighth edge sense amplifier blocks ESAB₁ andESAB₈, may be the farthest edge sense amplifier blocks from the mainsense amplifier group MSAG and are respectively disposed between thefirst dummy cell array block DCB₁ and the main cell array block MCB₁,and between the second cell array block DCB₂ and the main cell arrayblock MCB_(M), as illustrated in FIG. 1. Also, the second to seventhedge sense amplifier blocks ESAB₂-ESAB₇ may be disposed between the maincell array blocks MCB₁-MCB_(M), respectively. For example, the edgesense amplifier block ESAB₂ may be disposed between the main cell arrayblock MCB₁ and the main cell array block MCB₂.

As illustrated in FIG. 1, like the main sense amplifier blocksMSAB₁-MSAB₄, the first to eighth edge sense amplifier blocks ESAB₁-ESAB₈may include corresponding first to eighth sense amplifiers ESA₁-ESA₈.

Each of the first to eighth sense amplifiers ESA₁-ESA₈ may be connectedto corresponding first to eighth edge bit line pairs EBL₁-EBL₈ includingan edge bit line in the direction of the main sense amplifier group MSAGand an edge bit line in the opposite direction of the main senseamplifier group MSAG.

Each of the first to eighth sense amplifiers ESA₁-ESA₈ may be connectedto N+1 main cell array blocks by the edge bit line in direction of themain sense amplifier group MSAG. In addition, each of the first toeighth sense amplifiers ESA₁-ESA₈ may be connected to the main cellarray block and/or the dummy cell array blocks, DCB₁ and DCB₂ by itscorresponding edge bit line pair EBL₁-EBL₈. For example, the third edgesense amplifier ESA3 may be connected. The dummy cell array block DCB₁and the main sense amplifier group MSAG are disposed on opposite sidesof the first edge sense amplifier group ESAG₁. The dummy cell arrayblock DCB₂ and the main sense amplifier group MSAG are disposed onopposite sides of the second edge sense amplifier group ESAG₂. Senseamplifier less areas (SA_less area) SAL₁ and SAL₂, may be providedbetween the main sense amplifier group MSAG and the first edge senseamplifier group ESAG₁, and between the main sense amplifier group MSAGand the second edge sense amplifier group ESAG₂. Furthermore, when thereis a plurality of main sense amplifier groups MSAG, the sense amplifierless areas may be provided between each of the main sense amplifiergroups. Illustrated in FIG. 1, the first sense amplifier less areas SAL₁may be provided between the fifth and sixth main cell array blocks MCB₅and MCB₆, and between the tenth and eleventh main cell array blocksMCB₁₀ and MCB₁₁, which are disposed at both sides of the main senseamplifier group MSAG. Furthermore, the second sense amplifier less areasSAL₂ may be provided between the fourth and fifth main cell array blocksMCB₄ and MCB₅, and between the eleventh and twelfth main cell arrayblocks MCB₁₁ and MCB₁₂. In the example embodiment shown in FIG. 1, thesense amplifier less areas SAL₁ and SAL₂ may be defined as regions wheresense amplifier blocks are not disposed between the main cell arrayblocks. Also, the main cell array blocks MCB₁-MCB_(M) may havesubstantially the same number of memory cells and may be defined asregions where there are no disconnected bit line pairs. Therefore, themain cell array blocks MCB₁-MCB_(M) may have substantially the samewidth.

The widths of the first and second sense amplifier less areas SAL₁ andSAL₂ may be flexibly designed. Therefore, the first and second senseamplifier less areas SAL₁ and SAL₂ may enable a semiconductor designerto flexibly design a layout of integrated circuits necessary for asemiconductor device. For example, it is possible to minimize the sizeof the first and second sense amplifier less areas SAL₁ and SAL₂, and tothereby increase other areas. In addition, the first and second senseamplifier less areas SAL₁ and SAL₂ may provide a space to thesemiconductor designer, so that the designer may design an integratedcircuit capable of optimizing the performance of the semiconductordevice in the first and second sense amplifier less areas SAL₁ and SAL₂.

Meanwhile, a first dummy capacitor structure DCS₁ may be disposedopposite the first edge sense amplifier group ESAG₁ with the first dummycell array block DCB₁ interposed therebetween. Also, a second dummycapacitor structure DCS₂ may be disposed opposite the second edge senseamplifier group ESAG₂ with the second dummy cell array block DCB₂interposed therebetween. More specifically, the bit line of the firstedge bit line pair EBL₁ that is disposed in the direction of the mainsense amplifier group MSAG may be connected to the first to third maincell array blocks MCB₁-MCB₃, and the other bit line of the first edgebit line pair EBL₁ may be connected to the first dummy cell array blockDCB₁ and a first dummy capacitor C1 of the first dummy capacitorstructure DCS₁. When capacitors of the first dummy cell array block DCB₁connected to the first edge bit line pair EBL₁ have the same capacitanceas capacitors of one main cell array block connected to the first edgebit line pair EBL₁, the first dummy capacitor C1 may have a capacitancecorresponding to the other two blocks of the first to third main cellarray blocks MCB₁-MCB₃. Similarly, the bit line of the second edge bitline pair EBL₂ that is disposed in the direction of the main senseamplifier group MSAG may be connected to the second to fourth main cellarray blocks MCB₂-MCB₄, and the other bit line of the bit line pair EBL₂may be connected to the first main cell array block MCB₁, the firstdummy cell array block DCB₁ and a second dummy capacitor C2 of the firstdummy capacitor structure DCS₁. The second dummy capacitor C2 may have acapacitance corresponding to one block of the second to fourth cellarray blocks MCB₂-MCB₄. While each of the first and second dummycapacitors C1 and C2 may include a cell capacitor and/or a MOS capacitorincluding a lower electrode, a dielectric layer and an upper electrode,as disclosed in Korean Patent Registration No. KR-10-0575005, the firstand second dummy capacitors C1 and C2 may have different capacitances.The first and second dummy capacitors C1 and C2 may constitute the firstdummy capacitor structure DCS₁. Similarly, the third and fourth dummycapacitors C3 and C4 which may be disposed opposite the second edgesense amplifier group ESAG₂ with the second dummy cell array block DCB₂interposed therebetween. The third and fourth dummy capacitors C3 and C4may have different capacitances. The third and fourth dummy capacitorsC3 and C4 may constitute the second dummy capacitor structure DCS₂.Therefore, a capacitance of one side may be the same as that of theother side with respect to the first to fourth sense amplifiersESA₁-ESA₄, and the fifth to eighth sense amplifiers ESA₅-ESA₈,respectively, by the first and second dummy capacitor structures DCS₁and DCS₂.

At least one other example embodiment provides that the first and seconddummy cell array blocks DCB₁ and DCB₂ may be omitted. In each of thefirst and second dummy capacitor structures DCS₁ and DCS₂, another dummycapacitor may be laid out in an edge bit line pair selected among thefirst to fourth edge bit line pairs EBL₁-EBL₄, and the fifth to eighthedge bit line pairs EBL₅-EBL₈. The newly disposed dummy capacitor mayhave a capacitance corresponding to the omitted first and second dummycell array blocks DCB₁ and DCB₂.

The second main sense amplifier block MSAB₂ laid out between the seventhand eighth main cell array blocks MCB₇ and MCB₈ among theabove-described main cell array blocks MCB₁-MCB_(M) will be describedbelow with reference to FIG. 2.

Referring to FIG. 2, the second main sense amplifier block MSAB₂ mayinclude second main sense amplifiers MSA200, MSA201 and MSA202 arrangedin the column direction Y. Also, a plurality of main bit linesBL200-BL204 may be disposed across the seventh and eighth main cellarray blocks MCB₇ and MCB₈. The second main sense amplifier MSA 201 maybe laid out to be connected to one bit line pair BL201 and BLB201 andthe other main bit lines BL202 and BL203 may be laid out to cross overthe second main sense amplifier MSA201. However, it should be understoodthat any second main sense amplifier may be connected to a bit linepair.

Word lines WL201 and WL301 may be disposed across the seventh and eighthmain cell array blocks MCB₇ and MCB₈, respectively, and crossing themain bit lines BL200-BL204. A plurality of main cells MC300-MC304 may belaid out in the seventh main cell array block MCB₇, and a plurality ofmain cells MC400-MC404 may be laid out in the eighth main cell arrayblock MCB₈. Each of the main cells MC300-MC404 may have a MOS transistoras a cell switching device and a cell capacitor as a cell memory storagedevice.

Each of the main sense amplifiers may be laid out in every two or morebit line pitches as many as the number of main sense amplifier blocksconstituting the main sense amplifier group MSAG. For example, when thefirst to fourth main sense amplifier blocks MSAB₁-MSAB₄ are arranged inthe row direction X in one main sense amplifier group MSAG, each of thefirst to fourth main sense amplifiers MSA₁-MSA₄ may be laid out in everyfour bit line pitches in the column direction Y.

As described above, since the sense amplifier may be laid out in everytwo or more bit line pitches, a transistor constituting the senseamplifier can ensure the broad channel width. Accordingly, since an arealarge enough to lay out the sense amplifier is ensured, a reliable senseamplifier can be provided.

FIG. 3 illustrates a semiconductor device 3 according to another exampleembodiment. FIG. 3 is a layout illustrating that the locations of thesecond main sense amplifier block MSAB₂ and the third main senseamplifier block MSAB₃ of FIG. 1 may be changed. Also, the changedlocation of the second main sense amplifier block MSAB₂ of FIG. 1 tothat of the third main sense amplifier block MSAB₃ of FIG. 1 may causethe locations of the third edge sense amplifier block ESAB₃ of FIG. 1and the second edge sense amplifier block ESAB₂ of FIG. 1 to bechangeable and the locations of the sixth edge sense amplifier blockESAB₆ of FIG. 1 and the seventh edge sense amplifier block ESAB₇ to bechangeable. As a result of changing the locations of the second mainsense amplifier block MSAB₂ and the third main sense amplifier blockMSAB₃ of FIG. 1, locations of the second and fourth dummy capacitors C2and C4 of FIG. 1 constituting the first and second dummy capacitorstructures DCS₁ and DCS₂ may be changed to be laid out as illustrated inFIG. 3. As described above, since changing the locations of the secondand fourth dummy capacitors C2 and C4 in the example embodiments of FIG.3 is substantially similar as laying out the second and fourth dummycapacitors C2 and C4 in FIG. 1, the detailed descriptions thereof willbe omitted for the sake of brevity and clarity.

In addition, while not shown, the locations of the first and second mainsense amplifier blocks MSAB₁ and MSAB₂ of FIG. 1 may be changed.Similarly, the locations of the first and third main sense amplifierblocks MSAB₁ and MSAB₃ may be changed or the locations of the first andfourth main sense amplifier blocks MSAB₁ and MSAB₄ may be changed. Inthis case, when blocks selected from the first to fourth main senseamplifier blocks MSAB₁-MSAB₄ change their locations to be laid out, thelocations of the first to fourth edge sense amplifier blocks ESAB₁-ESAB₄and the fifth to eighth edge sense amplifier blocks ESAB₅-ESAB₈ may beappropriately changed to be laid out. Even though the locations of themain sense amplifier blocks of FIG. 1 may be changed to be laid out, thesense amplifier less areas SAL1 and SAL2 substantially similar to thatof FIG. 1 may be provided. In addition, the first to fourth main senseamplifiers MSA₁-MSA₄ may be laid out in every four bit line pitches inthe column direction Y as described above.

FIG. 4 illustrates a semiconductor device 4 according to another exampleembodiment.

The number of main sense amplifiers constituting one main senseamplifier group MSAG may be adjusted. For example, while the first tofourth main sense amplifier blocks MSAB₁-MSAB₄ may be sequentiallyarranged in FIG. 1, one of the first to fourth main sense amplifierblocks MSAB₁-MSAB₄ may be omitted as shown in FIG. 4. FIG. 1 illustratesthat one main sense amplifier group MSAG may include four main senseamplifier blocks, and FIG. 4 illustrates that one main sense amplifiergroup MSAG may include three main sense amplifier blocks. In FIG. 4, thefourth main sense amplifier block MSAB₄ may be omitted among the firstto fourth main sense amplifier blocks MSAB₁-MSAB₄ of FIG. 1. The omittedfourth main sense amplifier block MSAB₄ may cause the fourth edge senseamplifier block ESAB₄ and the eighth edge sense amplifier block ESAB₈ tobe omitted as well. Furthermore, as illustrated in FIG. 4, the first andsecond dummy bit lines DBL₁ and DBL₂ may be omitted. As described above,even though the fourth main sense amplifier block MSAB₄, the fourth edgesense amplifier block ESAB₄, the eighth edge sense amplifier blockESAB₈, and the first and second dummy bit lines DBL₁ and DBL₂ of FIG. 1may be omitted, the sense amplifier less areas SAL₁ and SAL₂ and anadditional sense amplifier less area SAL₃, may be provided between thememory cell blocks laid out at both sides of the main sense amplifiergroups MSAG. The number of sense amplifier less areas may be adjusteddepending on the number of main sense amplifier blocks constituting themain sense amplifier group MSAG and the number of “N”.

FIG. 5 illustrates a semiconductor device 5 according to another exampleembodiment. In FIG. 5, the second edge sense amplifier block ESAB₂, thesecond main sense amplifier block MSAB₂ and the seventh edge senseamplifier block ESAB₇ of FIG. 1 may be omitted. As a result of omittingthe second edge sense amplifier block ESAB₂, the second main senseamplifier block MSAB₂ and the seventh edge sense amplifier block ESAB₇,a fifth sense amplifier less areas SAL₅ may be provided within the firstedge sense amplifier group ESAG₁, the main sense amplifier group MSAGand the second edge sense amplifier group ESAG₂. In an alternativeembodiment, the fifth sense amplifier less areas SAL₅ may be omitted sothat main cell array blocks at both sides of the fifth sense amplifierless areas SAL₅ may be laid out like one cell array block.

FIG. 6 is a schematic block diagram of an electronic product employing asemiconductor device according to example embodiments.

Referring to FIG. 6, the electronic product 500 includes at least onememory device 503 for storing data and a processor 505 connected to thememory device 503. The memory device 503 may be the semiconductor deviceaccording to example embodiments. The electronic product 500 mayexchange data with other electronic systems such as personal computersor computer networks through an input/output unit 507. The input/outputunit 507 may provide data through a peripheral bus line of a computer, ahigh-speed digital transmission line or a wirelesstransmission/reception antenna. The data communication between theprocessor 505 and the memory device 503, and the data communicationbetween the processor 505 and the input/output unit 507 may be performedusing general bus architectures.

According to example embodiments, one sense amplifier can be laid out ina plurality of bit line pitches, and thus design rules of a senseamplifier can be flexible. Also, since an area large enough to disposethe sense amplifier can be ensured, the channel width of a transistorconstituting the sense amplifier can be increased. Therefore, a reliablesense amplifier can be provided.

While example embodiments have been described with reference to theexample embodiments shown in the figures, it should be understood thatother variations may be possible. Such variations are not to be regardedas a departure from the spirit and scope of example embodiments of thepresent application, and all such modifications as would be obvious toone skilled in the art are intended to be included within the scope ofthe following claims.

1. A semiconductor device comprising: a main sense amplifier groupincluding main sense amplifier blocks arranged in a row direction on asubstrate and spaced apart from each other; main cell array blocksarranged in the row direction on the substrate and spaced apart fromeach other; main bit line pairs configured to couple 2×(N+1) main cellarray blocks to each of the main sense amplifier blocks, each of themain sense amplifier blocks being disposed between the main cell arrayblocks and N is a positive integer; an edge sense amplifier group spacedapart from the main sense amplifier group, disposed at one side of themain sense amplifier group and arranged on the substrate, the edge senseamplifier group having edge sense amplifier blocks arranged in a rowdirection and spaced apart from each other and the edge sense amplifierblocks having edge sense amplifiers; at least one dummy cell array blockdisposed on a side of the edge sense amplifier group, the edge senseamplifier group being interposed between the at least one dummy cellarray block and the main sense amplifier group; and an edge bit linepair configured to couple at least one of N+1 main cell array blocks,the at least one dummy cell array block to at least one edge senseamplifier, at least one main cell array block to at least one edge senseamplifier, and the dummy cell array block to at least one edge senseamplifier.
 2. The device of claim 1, further comprising: a dummy bitline disposed on a virtual extension line of an edge bit line coupled tothe main cell array block of the edge bit line pair, and configured tocouple the dummy cell array block, wherein the dummy bit line is spacedapart from the edge bit line pair.
 3. A semiconductor device comprising:a main sense amplifier group including main sense amplifier blocksarranged in a row direction on a substrate and spaced apart from eachother; main cell array blocks arranged in the row direction on thesubstrate and spaced apart from each other; main bit line pairsconfigured to couple 2×(N+1) main cell array blocks to each of the mainsense amplifier blocks, each of the main sense amplifier blocks beingdisposed between the main cell array blocks and N is a positive integer;an edge sense amplifier group spaced apart from the main sense amplifiergroup, disposed at one side of the main sense amplifier group andarranged in a row direction on the substrate, the edge sense grouphaving edge sense amplifier blocks spaced apart from each other and theedge sense amplifier blocks having edge sense amplifiers; at least onedummy capacitor group disposed on a side of the edge sense amplifiergroup, the edge sense amplifier group being interposed between the atleast one dummy capacitor group; and an edge bit line pair configured tocouple at least one of N+1 main cell array blocks, the at least onedummy capacitor group to at least one edge sense amplifier, and the maincell array block to at least one edge sense amplifier.